The good alternative was to use the AXI Data Mover. – The transfer commands are delivered by AXI4 Stream. – The status of transfers are delivered back by. The AXI Datamover is a key Interconnect Infrastructure IP which enables high throughput transfer of data between AXI4 memory mapped domain to AXI4- Stream. For you, you are probably looking at AXI Datamover or AXI Central DMA. ” Xilinx provides the AXI Virtual FIFO Controller core to use external.
|Published (Last):||14 October 2014|
|PDF File Size:||6.33 Mb|
|ePub File Size:||3.51 Mb|
|Price:||Free* [*Free Regsitration Required]|
Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. I suspected that there might be something wrong with the command word I am sending but the logic analyzer data tells me otherwise from what I could tell. I changed my HDL code for testing purposes. We have detected your current browser version is not the latest one.
I am on a similar project but need a little bit more time to tell if it works as expected. I’m facing a similar situation and I’m curious to see how you fixed it. I’m not quite sure why that is happening.
It is illegal for the core to deassert tvalid until tready accepts it. Please upgrade to a Xilinx. Embedded Processor System Design: We have detected your current browser version is not the latest one. From what it seems, the datamover is not accepting anymore data over the AXIS bus after a few clock cycles. If you don’t use the sts busses inside your design i.
Please upgrade to a Xilinx. The command word settings are as follows: I connected manually each signal from two AXI interfaces from datamover to each signal in one AXI interface and it worked so the rest of my design is finebut I dubt it’s a good practise. I would really appreciate more insights getting the datamover to work has been really frustrating.
We have detected your current browser version is not the datmaover one. Currently I have the command word set for fixed address which I am doing until I get the design to work.
Solved: difference between AXI Datamover and AXI DMA – Community Forums
Here is what I am trying to do with my design: I finally managed to get some more insights on what is happening. I am trying to create a design using the AXI datamover in a Zynq design using a zedboard yet I am really struggling.
Revision History The following table shows the revision history for this document. I found out that I was also trying the same configuration, but haven’t been able to test it because the Datamover Steam Data Width Auto is stuck at 32 even though I have a bus connected to it.
AXI Datamover Design Problem – Community Forums
The is still a problem though. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http: I recognize that I am writing the dafamover all to the same location so I would see the last value I would write, but that is not happening either. I have a state machine running for the data that would send a bit data word datakover time a new value becomes available.
All forum topics Previous Topic Next Topic. All other trademarks are the property of their respective owners.
The VHDL code now does the following:. ChromeFirefoxInternet Explorer 11Safari.
AXI interconnect and DataMover. After a all the Chipscope issues, I decided to start a clean slate project in Vivado and try datamoverr the logic analyzer instead. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.
As I am connecting a normal fifo to this input, which is not master axi, then I created an Datamocer fifo, with the correct width, validate, erase and finally with the correct width connect my normal fifo in the place I had it before.
It’s the mechanism to propagate various parameters like data width.